EURASIP Journal on Embedded Systems
Energy Efficient Architectures for Embedded Systems
Sept. 20, 2015 (closed)
This special issue is mainly focused on the new design and development trends of energy efficient processing architectures for embedded systems. Topics of interest cover all aspects of this research domain, including not only architectures and specific design methods, but also more technological aspects related to micro-architecture design, memory hierarchies, communication mechanisms and tools/algorithms for energy/power management and control.
A significant boost in embedded computing systems performance has been observed at several different domains, mostly due to technology scaling and to the ever increasing exploitation of parallel processing architectures.
However, although conventional approaches relying on homogeneous/heterogeneous chip-multiprocessor aggregates already allow achieving a significant performance level, important compromises have to be established in order to cope with the strict energy efficiency requirements imposed at the several different embedded application domains (e.g. mobile, battery supplied and hand-held devices).
As a consequence, energy efficiency is gradually becoming one fundamental constraint and requisite for embedded systems design, often requiring the adoption of new technologies and micro-architecture design approaches.
Topics of interest include:
- Computer architecture trends for energy efficiency in embedded systems (heterogeneous parallel processing architectures; ISA diversity (e.g. scalar/vector/VLIW/SMT) and morphable structures; run-time reconfiguration/adaptation and dynamic scalability; CPU-accelerator co-design: embedded GPUs, APUs, FPGAs, etc.; approximate computing techniques and architectures)
- Energy/power management and control (run-time power/energy monitoring and
- sensing; heat/power/energy models of embedded architectures; Dynamic Voltage and Frequency Scaling (DVFS) and power/clock gating strategies; performance vs. power/ energy scaling and management)
- Energy efficient memory hierarchy subsystems (caches and TLB organizations; memory management policies; data reuse schemes; pre-fetching and data streaming)
- Energy efficient communication and data-transfer subsystems (network on chip with energy efficiency constraints; embedded networking and routing; input/output peripheral interfaces)Tools and algorithms (models for energy-aware computing; simulation tools for heat/power/energy estimation; scheduling and task/thread migration policies for energy efficiency; operating system support and energy management tools)
- Technologies and energy-aware solutions for embedded systems (embedded processors and clusters (e.g. ARM’s big.LITTLE); embedded GPUs (e.g., NVIDIA’s Tegra, ARM’s Mali, Imagination Technologies’ PowerVR); embedded SoCs and FPGAs (e.g. Xilinx’s Zynq, Altera’s Cyclone)
Lead Guest Editor
- Nuno Roma, INESC-ID, Instituto Superior Técnico, Universidade de Lisboa
- Jose Luis Nunez-Yanez, University of Bristol